1. Field of the Invention
The present invention relates to digital cameras and, more particularly, to a digital camera which transfers through a bus image to be processed or having been processed through DMA (Direct Memory Access) (DMA Processed Data) and the image data to be processed or having been processed through CPU (CPU Processed Data).
2. Description of the Related Art
In the conventional digital cameras of this kind, where displaying real-time motion pictures, for example, on a monitor, the image data transferred from the CCD imager through a bus is processed by DMA and outputted to the monitor through the bus. On the other hand, where recording still picture data onto a recording medium responsive to operation of the shutter button, the still picture data upon pressing the shutter button is processed by the CPU and outputted to the recording medium via the bus. In these operations, the DMA processed data and the CPU processed data are transferred through the common bus.
However, if the common bus is used in transferring high-speed DMA processed data and low-speed CPU processed data, one of the data adversely affects the other, thus resulting in a problem of reducing operational efficiency. That is, there has been a case that CPU processing is delayed as a result of a high occupation ratio over the bus or DMA processed data is prevented from transferring by the reduction in CPU processing speed.
Therefore, it is a primary object of this invention to provide a digital camera which is capable of processing data with efficiency.
In accordance with the present invention, a digital camera, comprises: a picture taking means for taking a picture of a photographic subject and outputting image data; a display means for displaying an image corresponding to the image data; a compression means for compressing the image data and outputting compressed image data; a first bus for connecting between said picture taking means, said display mean sand said compression means; a main memory; an access means connected to said first bus and making access to said main memory through DMA to write/read the image data and the compressed image data; a second bus; a bus bridge for connecting between said first bus and said second bus as required; and a CPU connected to said second bus and preforming a predetermined processing on the compressed image data according to a program.
The image data outputted from the picture taking means is supplied to the access means through the first bus, and written to the main memory through DMA by the access means. The image data written on the main memory is thereafter read through DMA by the same access means, and supplied through the first bus onto the display means. As a result, an image is displayed corresponding to the image data. The image data read out by the access means also is supplied through the first bus to the compression means. The compression means compresses the given image data to output compressed image data. The compressed image data output is given to the access means via the first bus, and written to the main memory through DMA. The compressed image data is thereafter read out by the access means, and supplied to the CPU via the second bus. The CPU processes the compressed image data thus given according to a predetermined program.
According to this invention, DMA processed data is transferred using the first bus whereas CPU processed data is transferred with the second bus, thus enabling data processing with efficiency.
In one aspect of the present invention, if an instruction to record image data is inputted by the record instruction input means, the CPU disables the picture taking means and enables the compression means in response to this record instruction. The CPU further turn on the bus bridge to fetch the compressed image data onto the second bus side and record the compressed image data in the recording medium.
In another aspect of the present invention, the second bus is connected with a focus control means and a strobe control means. The focus control means controls on focusing according to an instruction by the CPU, while the strobe control means controls strobe also according to a CPU instruction.
In still another aspect of the present invention, the data output means is connected to the second bus so that this data output means outputs the compressed image data to an outside, according a CPU instruction.
In a further aspect of the present invention, the image data taken by the picture taking means is stored through DMA to the first buffer connected to the first buffer. Also, the image data read from the main memory is temporarily held in the second buffer and thereafter read out through DMA. The read image data is outputted onto a monitor, resulting in displaying a corresponding image on the monitor. The image data read from the main memory also supplied through a third buffer to the compression processing means where it is subjected to a predetermined compression processing. The obtained compressed image data is supplied through a fourth buffer to an access means so that it is stored in the main memory.
In one embodiment of the present invention, the access means includes a buffer access means and a main memory access means. The buffer access means makes access to the first to fourth buffers through DMA. The main memory access means also makes access to main memory through DMA. That is, the buffer access means reads the image data from the first buffer in response to a read request from the picture taking means, and writes the image data to the second buffer in response to a write request from a display means. The buffer access means also writes the image data to the third buffer in response to a write request from a third request output means included in the compression means, and reads the compressed image data from the fourth buffer in response to a read request from a fourth request output means.
The access means further includes an on/off means to turn on/off the bus bridge. If an image data record instruction is inputted by a record instruction input means, the CPU disables the first request output means and enables the third request output means, in response to the record instruction. The CPU further causes the on/off means to turn on the bus bridge, and requests the access means to read the compressed image data. The compressed image data read out of the main memory by the access means is supplied to the CPU via the second bus.